![]() The Precise-ITC Ethernet packet generator and monitor in the FPGA are used to generate full rate 400Gb/s traffic. The capabilities of the Precise-ITC 400GE PCS and MAC with KP4 FEC will also be demonstrated. ![]() ![]() The demonstration will show loop-back testing between the Intel Stratix 10 FPGA and the eSilicon SerDes running at 53.125Gb/s in PAM4. 400Gb/s Forward Error Correction (FEC) for the demo is implemented with the Precise-ITC E-pak 400G core instantiated in the Intel Stratix 10 FPGA. The demonstration verifies interoperability between eSilicon’s 56G PAM4 & NRZ DSP-based long-reach 7nm SerDes and the SerDes embedded in an Intel® Stratix® 10 FPGA. SAN DIEGO, Ma(GLOBE NEWSWIRE) - eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today at the OFC conference in San Diego an interoperability demonstration in their booth #5416. Interoperability demonstrated between eSilicon 7nm SerDes and Intel Stratix 10 FPGA A Scalable 9σ Additive White Gaussian Noise (AWGN) Generator.SONET/SDH : OC12/4xOC3 | STM-4/4xSTM-1 Framer.1G-100G Ethernet/FiberChannel/FlexO Core.10G-400G Ethernet/FiberChannel/FlexO Core.10G-800G Ethernet/FiberChannel/FlexO Core.10G-1.6T Ethernet/FiberChannel/FlexO Core.
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